AMC Dual DAC 14-bit @ 5.7 GSPS Module

The AMC529 is a dual port DAC module with 14-bit at 2.85 GSPS direct RF synthesis. 

It has a Virtex-7 FPGA with 3 banks of 144 Mbit QDR-II+ memory (36-bit wide) and 2 Gbit DDR3 memory (16-bit wide).

The DAC converter utilizes the Analog Devices AD9129. The chip core is based on a quad-switch architecture that enables dual-edge clocking operation, effectively increasing the DAC update rate to 5.7 GSPS when configured for Mix-Mode™ or 2x interpolation. The high dynamic range and bandwidth enable multi-carrier generation up to 4.2 GHz.

The Module has option to have the direct RF sampling clock come through the front panel or using the on board wide-band PLL to do the clock synthesis. The front panel allows for user I/O.

Benefits

  • Highest performance DAC speed available in AMC format at time of development
  • Excellent dynamic and direct RF synthesis performance with minimal loss in output power
  • Ideal for Broadband communications systems, Wireless infrastructure, LTE, ATE, RADAR/Jamming
  • Electrical, mechanical, software, and system-level expertise in house
  • Full ecosystem of front and rear boards, enclosures, specialty modules, and test/dev products from one source
  • AS9100 and ISO9001 certified company
  • AMC single module, mid-size (full-size optional)
  • Dual port DAC 14-bit at 5.7 GSPS (2.85 GSPS direct RF synthesis)
    • DC-to-1.4 GHz in Baseband mode
    • DC-to-1.0 GHz in 2x Interpolation mode
    • 1.4 to 4.2 GHz in Mix-Mode
  • Xilinx Virtex-7 690T FPGA in FFG-1761 package
  • AMC Ports 4-11 are routed to FPGA per AMC.1, AMC.2 and AMC.4 (protocols such as PCIe, SRIO, XAUI, etc. are FPGA programmable)

Key Features

  • AMC single module, mid-size (full-size optional)
  • Dual port DAC 14-bit at 5.7 GSPS (2.85 GSPS direct RF synthesis)
    • DC-to-1.4 GHz in Baseband mode
    • DC-to-1.0 GHz in 2x Interpolation mode
    • 1.4 to 4.2 GHz in Mix-Mode
  • Xilinx Virtex-7 690T FPGA in FFG-1761 package
  • AMC Ports 4-11 are routed to FPGA per AMC.1, AMC.2 and AMC.4 (protocols such as PCIe, SRIO, XAUI, etc. are FPGA programmable)
  • AMC Ports 12-15 and 17-20 are routed to the FPGA
  • AMC FCLKA, TCLKA, TCLKB, TCLKC and TCLKD are routed
  • Clock jitter cleaner and on board clock generation
  • Front panel direct RF clock sampling
  • Excellent dynamic performance
  • Front panel interface includes CLK In, Trig In/Out, Analog Out, and GPIO
  • Three banks of high speed QDRII+ (432 Mbit total x36)
  • RoHS compliant
  • IPMI v2.0
 
 
 
 
 

 

 

 

 

Datasheet

 
Fonte - VadaTech
 
27 de abril de 2015