Highest Performance FPGA and SoC at 20 nm
Arria 10® FPGAs and SoCs deliver the highest performance at 20 nm offering a one speed-grade performance advantage over competing devices. Arria 10 FPGAs and SoCs are up to 40 percent lower power than previous generation FPGAs and SoCs and feature the industry’s only hard floating-point digital signal processing (DSP) blocks with speeds up to 1,500 giga floating-point operations per second (GFLOPs).
Highest Performance at 20 nm with Arria 10 FPGAs and SoCs:
- One speed grade faster than competing FPGAs and SoCs
- The industry’s only midrange 28.3 Gbps support
- Highest performance 2,666 Mbps DDR4 SDRAM memory interface
- IEEE 754-compliant hard floating-point with 1,500 GFLOPS of DSP performance
- 96 transceiver lanes deliver 3.6 Tbps of serial bandwidth
Up to 40 Percent Lower Power Than the Previous-Generation FPGAs and SoCs
- Programmable Power Technology – reduce device power in lower performance circuits while also delivering highest performance where needed
- Smart voltage ID – operate devices to run optimum lower voltage without impacting performance
- VCC power manager – operate devices at multiple voltage levels for either higher performance or lower power
- Low static power grades – select devices with lower maximum static power
Industry’s Only 20 nm ARM-Based SoC
- Multiple SoC choices with dual-core ARM® Cortex®-A9 MPCoreTM hard processor system (HPS)
- 1.5 GHz CPU operation per core
- Move existing Arria V SoC designs in 28 nm to Arria 10 SoC with no changes to processor code
Save Board Space with Integration
- 2X more density versus the previous generation midrange with over 1 million logic elements (LEs)
- Hard intellectual property (IP) cores: DDR4 memory controllers and PCI Express® (PCIe®) 3.0 specification (Gen3)
- Enpirion® PowerSoCs offer customers the smallest footprint, highest performance, lower system power, higher reliability and efficiency, and faster time-to-market to power Arria 10 FPGAs and SoCs
Increase Productivity and Decrease Time to Market with Altera’s Quartus II Software
- Industry’s fastest compile time at 20 nm and most advanced design environment
- Best-in-class IP cores including 100G Ethernet, 100G Interlaken, and PCIe Gen3, with 2X performance and lower latency
- Industry-leading compile times using this software release (an average of 2.5X faster than the nearest competitor’s software), enabling faster design iterations and faster timing closure
- C-based design entry using the Altera® SDK for OpenCLTM, offering a design environment that is easy to implement on FPGAs
- System-level design environment with Qsys system integration tool
- DSP Builder – a model-based DSP environment within the MATLAB/Simulink environment
Table 1. Arria 10 Variants
| Variant | Description |
|---|---|
| Arria 10 GT | FPGAs enabled with up to 96 full-duplex transceivers with data rates up to 28.3 Gbps chip-to-chip, 17.4 Gbps backplane and up to 1,150K equivalent LEs |
| Arria 10 GX | FPGAs enabled with up to 96 full-duplex transceivers with data rates up to 17.4 Gbps chip-to-chip, 16.0 Gbps backplane, and up to 1,150K equivalent LEs |
| Arria 10 SX | SoCs enabled with a dual-core ARM Cortex-A9 HPS, up to 48 full-duplex transceivers with data rates up to 17.4 Gbps chip-to-chip, 16.0 Gbps backplane, and up to 660K equivalent LEs |
Fonte - Altera Corporation
04 de marco de 2015
