This module features two 105MHz 16-bit A/D channels. An external clock and trigger can be used to control sampling.
An internal precision clock conditioner provides the functions of jitter cleaning/reconditioning, multiplication, and distribution of a reference clock.
Each clock distribution block includes a programmable divider, a phase synchronization circuit, and a programmable delay. This allows multiple integer-related and phase-adjusted copies of the reference to be distributed to multiple system components.
• Operating temperature: 0 to 70°C
Analog Input
• Input configuration: Two differential channels using two Analog Devices AD9460 A/D converter.
• A/D resolution: 16 bits.
• Input range: 3.4V peak-to-peak, centered at 0V, into a 50 ohm load.
• External clock input: 3.3V peak-to-peak.
• Input clock range:1-105MHz.
• Maximum throughput rate:
1 channel (max.): 9.5nS (105MHz).
2 channels (max.): 9.5nS (105MHz).
A/D trigger: External source, FPGA controlled.
• Input clock controller:Precision clock conditioner combines the functions of jitter cleaning/reconditioning, multiplication, and distribution of a reference clock.
• Signal-to-noise ratio: 69dB (25°C) typical.
• Signal-to noise and distortion: 67dB (25°C) typical.
• General purpose I/O: Low voltage TTL.
Physical Dimensions
Size: 11.5 mm high x 31.0 mm deep x 74.0 mm wide (0.453 inches x 1.220 inches x 2.913 inches)
Stacking height: 5.0 mm (0.197 inches).
Complies with PMC Specification P1386.1 for a single-width PMC module when installed on a supported PMC module.
Connectors
Front field I/O: Four SMA PCB jack female receptacle connectors.
FPGA Design for Flexible, High-Speed I/O Contro
Learn about fpga-based system design for embedded computing I/O signal processing applications. This video discusses how Advanced Xilinx Virtex and Altera Stratix FPGAs make use of multiple digital clock managers and simultaneous parallel execution to rapidly compute a set of integrated processes including FFT, SERDES, FIFO management, logic sequencing, DDR control, and more. With integrated I/O and enablers such as a soft CPU and IP cores, plus tools such as Xilinx ISE, Altera Quartus, SimuLink, and MathLab; the FPGA can process logic much faster than any real-time system with less effort than ever before.
Fonte - Acromag
