Altera reveals product details of its Stratix 10 FPGAs and SoCs, delivering performance, integration, density and security.
Stratix 10 FPGAs and SoCs use Altera’s HyperFlex FPGA fabric architecture built on the Intel 14 nm Tri-Gate process to provide 2X higher core performance over previous generation FPGAs. GPU-class floating point computation performance and heterogeneous 3D SiP integration, enables users to address design challenges in the next generation of communications, data center, IoT infrastructure, military and high-performance computing systems.
Stratix 10 FPGAs and SoCs are the first Altera devices to leverage the company’s new HyperFlex architecture. HyperFlex architecture introduces registers throughout all core interconnect routing segments, enabling Stratix 10 FPGAs and SoCs to benefit from performance-enhancing design techniques such as register retiming, pipelining and other design optimisation techniques.
The HyperFlex architecture allows designers to eliminate critical paths and routing delays, and close timing on their designs. The ability to achieve 2X higher core logic performance also enables dramatic improvements in device utilisation and power by reducing the need for very wide data paths and other skew-inducing design constructs. HyperFlex architecture also enables high-performance designs to operate up to 70 percent lower power by reducing logic area requirements.
All members of the Stratix 10 FPGA and SoC family leverage heterogeneous 3D SiP integration to efficiently and economically integrate a high-density monolithic FPGA core fabric (up to 5.5M logic elements) with other advanced components, thereby increasing scalability and flexibility. A monolithic core fabric maximises device utilisation and performance by avoiding the connectivity issues of competing homogeneous devices that use multiple FPGA die to deliver higher densities. Altera’s heterogeneous SiP integration is enabled through the use of Intel’s EMIB (Embedded Multi-die Interconnect Bridge) technology.
Initial Stratix 10 devices will use EMIB to integrate high-speed serial transceiver and protocol tiles with monolithic core logic. Implementing high-speed protocols and transceivers through a heterogeneous 3D SiP approach will allow Altera to deliver Stratix 10 device variants that address evolving market demands. For example, the use of heterogeneous 3D SiP integration provides Stratix 10 devices a path to support higher transceiver rates (56 Gbps), emerging modulation formats (PAM-4), communications standards (PCIe Gen4, Multi-Port Ethernet), and other capabilities such as analogue or high-bandwidth memory.
All densities in the Stratix 10 family will be available with an integrated 64-bit ARM quad-core Cortex-A53 hard processor system (HPS) with a rich feature set of peripherals, including a system memory management unit, external memory controllers and high-speed communication interfaces.
