High-Speed RT FPGAs for Signal Processing Applications

RTG4 - High-Speed RT FPGAs for Signal Processing Applications

RTG4 FPGAs integrate Microsemi’s fourth-generation flash-based FPGA fabric and high-performance interfaces such as serialization/deserialization (SERDES) on a single chip while maintaining the resistance to radiation-induced configuration upsets in the harshest radiation environments, such as space flight (LEO, MEO, GEO, HEO, deep space); high altitude aviation, medical electronics, and nuclear power plant control.


   

Configuration Immunity

 

RTG4 FPGAs are manufactured on a low power 65nm process with substantial reliability heritage. RTG4 FPGAs will be qualified to MIL-STD-883 Class B, and Microsemi will seek QML Class Q and Class V qualification.

RTG4 FPGAs are immune to radiation (SEU) induced changes in configuration, due to the robustness of the flash cells used to connect and configure logic resources and routing tracks.

No background scrubbing or reconfiguration of the FPGA is needed in order to mitigate changes in configuration due to radiation effects. Data errors, due to radiation, are mitigated by hardwired SEU resistant flip-flops in the logic cells and in the mathblocks. Single Error Correct Double Error Detect (SECDED) protection is optional for the embedded SRAM (LSRAM and uSRAM) and the DDR memory controllers. This means that if a one-bit error is detected, it will be corrected. Errors of more than one bit are detected only and not corrected. SECDED error signals are brought to the FPGA fabric to allow the user to monitor the status of these protected internal memories.

RTG4 Product Features  RT4G075 RT4G150
Logic / DSP Maximum Logic Elements (LUT4 + TMR flip-flop) 77,712 151,824
Mathblocks (18-bit x 18-bit) 224 462
Radiation-Tolerant PLLs 8 8
Memory  LSRAM 24.5 kbit Blocks (with ECC) 111 209
uSRAM 1.5 kbit Blocks (with ECC) 112 210
Total SRAM Mbits 2.8 5.3
uPROM Kbits 254 381
High-Speed Interface SERDES lanes (3.125 Gbit/sec) 16 24
PCIe Endpoints 2 2
DDR2/3 SDRAM Controller (with ECC) 2x32 + 4 bits ECC  2x32 + 4 bits ECC 
SpaceWire Clock & Data Recovery Circuits 16 16
User I/Os MSIO (3.3 V) 156 240
MSIOD (2.5 V) 192 300
DDRIO (2.5 V)  180 180
User IO (excluding SERDES) 528 720
Packages    CCGA/CLGA 1432 CCGA/CLGA 1657
CCGA/CLGA 1657

RTG4 Development Kit

The RTG4 Development Kit provides space customers with an evaluation and development platform for applications such as data transmission, serial connectivity, bus interface and high speed designs using RTG4 Radiation-Tolerant High-Density High-Performance FPGAs.  The development board features a RT4G150 device offering more 150,000 logic elements in a Ceramic package with 1,657 pins.
 

Hardware Features

 

The RTG4 Development Kit board includes the following features:

  • Two 1GB DDR3 synchronous dynamic random access memory (SDRAM)
  • 2GB SPI flash memory
  • PCI Express Gen 1 x1 interface
  • PCIe x4 edge connector
  • One pair SMA connectors for testing of the full-duplex SERDES channel
  • Two FMC connectors with HPC/LPC pinout for expansion
  • RJ45 interface for 10/100/1000 Ethernet
  • USB micro-AB connector
  • Headers for SPI, GPIOs
  • FTDI programmer interface to program the external SPI flash
  • JTAG programming interface
  • RVI header for application programming and debug
  • Flashpro programming header
  • Embedded trace macro (ETM) cell header for debug
  • Dual in-line package (DIP) switches for user application
  • Push-button switches and LEDs for demo purposes
  • Current measurement test points