MAX10 FPGA Single Chip Non-Volatile Programmable Logic Solutions - com vídeo
What sets MAX® 10 apart is the inclusion of features such as analogue blocks, embedded Flash and dual configuration images. In addition, unlike previous families of FPGA, MAX® 10 FPGA’s are a true single chip solution, requiring no external configuration device.
Building upon the single chip heritage of previous MAX device families, densities range from 2k...50k LE, using either single or dual supply rails. The MAX® FPGA family also encompasses both small packaging and high I/O pin count packages.
MAX® 10 FPGAs are built on TSMC’s 55 nm embedded flash technology, enabling instant-on functionality so users can quickly control power-up or initialization of other components in the application such as in system management applications.
The dual-image configuration Flash allows users to store and dynamically switch between two images on a single chip. Alternatively the second image space may be used as part of a user design. The sleep mode feature provides up to 95% savings of dynamic power. This feature set gives MAX® 10 FPGAs a unique level of integration in the low-cost FPGA space.
By putting more functions into a single programmable logic device, customers can lower their total system cost and increase their products reliability with a reduced component count increasing system integration
For industrial and automotive systems, the MAX® 10 FPGA single-chip integration, including Nios® II processor support, provide a reduced footprint with increased design security and product reliability while lowering system cost.
- Up to 50k logic elements (LE)
- Wide I/O count range: 27 to 500 I/Os
- Wide package range: 3 x 3 mm2 to 27 x 27 mm2
- Non-volatileiInstant on operation
- Embedded user and dual configuration Flash memory
- Embedded SRAM
- Remote update support
- Analogue blocks: 2 x 12-bit SAR ADC
- Internal temperature sensor
- Single chip
- Dual and single power supply options
- Embedded processor support
- DDR3/L memory support
- Phase locked loops: up to four
- Sleep mode for reduced dynamic power
- Design security: 128-bit AES
- Unique ID for each device
- Lower time to market, lower cost
- Long lifecycles
- Industrial drives
- Motor control
- I/O modules
- Networking
- Communications
- Computing and storage
- Automotive Infotainment
- ADAS
- E-vehicle
- Intelligent platform management interface (IPMI)
- FPGA solutions


