Microsemi's new SmartFusion2 SoC FPGAs: Security – Reliability – Low Power - com vídeo

Microsemi’s next-generation SmartFusion2 SoC FPGAs are the only devices that address fundamental requirements for advanced security, high reliability and low power in critical industrial, military, aviation, communications and medical applications. 

SmartFusion2 integrates an inherently reliable flash-based FPGA fabric, a 166 megahertz (MHz) ARM® Cortex™-M3 processor, advanced security processing accelerators, DSP blocks, SRAM, eNVM, and industry-required  high-performance communication interfaces all on a single chip.

SmartFusion2 Architecture

SmartFusion2 SoC FPGA is a mix of hard IP blocks and FPGA on a single die. By leveraging hard IP within the device we can maximize the functional resources common to many systems in minimal silicon space, while offering full flexibility for design customization with the FPGA fabric and firmware. The Microcontroller Subsystem (MSS) has multiple interfaces to the FPGA, to allow for peripheral expansion and algorithm acceleration in the fabric. By using a flash process we can include embedded nonvolatile memory for data and code storage, and have significant advantages in design and data security.

SmartFusion2 integrates for the first time non volatile flash based FPGA with a full feature Microcontroller subsystem, enhanced FPGA fabric and high speed serial and memory interfaces. The FPGA fabric composed of 4-input LUT logic elements, includes embedded memories and mathblocks for DSP processing capabilities. The Microcontroller subsystem adds the Embedded Trace Macrocell, instruction cache and includes USB, CAN and gigabit Ethernet. High speed serial interfaces with up to 4 SERDES lanes supports PCIe, XAUI and Native SERDES interfaces and up to two high speed DDR memory interfaces are included supporting LPDDR, DDR2 and DDR3.

• 166MHz ARM® Cortex™-M3 w/ on chip eSRAM & eNVM
  • Includes ETM and Instruction Cache
  • Extensive peripherals CAN, TSE, USB
• Most Secure FPGA
• DPA Hardened, AES256, SHA256, Random Number Generator
• SEU Immune Zero FIT Flash FPGA Configuration Cells
• SEU Protected Memories: eSRAMs, DDR Bridges (MSS, MDDR, FDDR), Instruction Cache, Ethernet, CAN and USB Buffers, PCIe, MMUARTand SPI FIFOs
• Hard 800 mbps DDR2/3 controllers with SECDED (also called EDAC) protection
• Built in Self Test
• 1mW in flash-freeze mode
• 10mW static power during operation
• Most Reliable FPGA
• Lowest Power FPGA
• 2x Fabric performance
• 16x 5Gbps SERDES, PCIe, XAUI / XGXS+ Native SERDES
• Integrated DSP processing blocks
• 120K LUT, 5Mbit SRAM, 4Mbit eNVM

System designers can leverage the newly released, easy-to-use Libero® system-on-chip (SoC) software toolset for designing SmartFusion2 devices. Libero SoC integrates industry leading synthesis, debug and DSP support from Synopsys, and simulation from Mentor Graphics with power analysis, timing analysis and push button design flow. Firmware development is fully integrated into Libero SoC with compile and debug available from GNU, IAR and Keil, and all device drivers and peripheral initialization is auto generated based on System Builder selections. Operating system support includes uClinux from EmCraft Systems, FreeRTOS, SAFERTOS and uc/OS-III from Micrium.

Starter Kit

Datasheet